Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory, among others.
Flash memory devices are utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.
Uses for flash memory include memory for personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices. This information can be used in personal computer systems, among others.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged
A NAND array architecture arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are coupled by rows to word select lines. However each memory cell is not directly coupled to a column bit line by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a source line and a column bit line.
Memory cells in a NAND array architecture can be configured, e.g., programmed, to a desired state. That is, electric charge can be placed on, or removed from, the floating gate of a memory cell to put the cell into a number of stored states. For example, a single level cell (SLC) can represent two binary states, e.g., 1 or 0. Flash memory cells can also store more than two binary states, e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110. Such cells may be referred to as multi state memory cells, multibit cells, or multilevel cells (MLCs). MLCs can allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one bit. MLCs can have more than one programmed state, e.g., a cell capable of representing four bits can have fifteen programmed states and an erased state.
MLC memory stores multiple bits on each cell by using different threshold voltage (Vt) levels for each state that is stored. The difference between adjacent Vt distributions may be very small for a MLC memory device as compared to a SLC memory device. The reduced margins between adjacent Vt distributions, e.g., program states, can increase the difficulty associated with distinguishing between adjacent program states, which can lead to problems such as reduced data retrieval reliability.
For example, various data degradation mechanisms exist which can cause the Vt level of a cell to shift such that the Vt level no longer corresponds to a desired Vt distribution, e.g., program state, for the cell. Data degradation mechanisms can affect the Vt levels of cells at various times such as during programming and/or reading of the data stored by a memory cell. Data degradation mechanisms can include program disturb mechanisms, program verify and/or read disturb mechanisms, and charge loss mechanisms, to name a few.
Some such data degradation mechanisms can have systematic effects on cells of a given row, e.g., word line, of a memory array. The systematic effects can occur on a group basis, e.g., on groups of cells such as pages and/or sectors of cells on a word line that can be programmed and/or read together. That is, some degradation mechanisms can cause a Vt shift of groups of cells on a word line in a systematic manner. For instance, some program and/or read disturb mechanisms can cause the Vt levels of a group of cells on a particular word line to shift by particular voltage amounts, e.g., 20 mV, 50 mV, 100 mV, or 200 mV, on a relatively consistent basis. In some cases, a systematic Vt level shift associated with the group of cells may depend on the desired program state, e.g., the Vt level shift may be different for program states corresponding to higher target Vt levels than for program states corresponding to lower target Vt levels.
Memory cells affected by data degradation mechanisms can become unreliable, e.g., the logical value read from the cells may not necessarily be the logical value written to the cells.